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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Freescale Semiconductor, Inc.Order Number: MC100ES6226/D
Rev 1, 12/2001
2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider
The Motorola MC100ES6226 is a bipolar monolithic differential clock distribution buffer and clock divider. Designed for most demanding clock distribution systems, the MC100ES6226 supports various applications that require a large number of outputs to drive precisely aligned clock signals. Using SiGe technology and a fully differential architecture, the device offers superior digitial signal characteristics and very low clock skew error. Target applications for this clock driver are high performance c l oc k dis t r ibut io n s y s te ms fo r c o m p u ti n g , netw ork i ng and telecommunication systems.
MC100ES6226
2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DIVIDER
Freescale Semiconductor, Inc...
* * * * * * * * * *
Features: Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Selectable 1:1 or 1:2 frequency outputs LVPECL compatible differential clock inputs and outputs LVCMOS compatible control inputs Single 3.3V or 2.5V supply Max. 35 ps maximum output skew (within output bank) Max. 50 ps maximum device skew Supports DC operation and up to 3 GHz (typ.) clock signals
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
Synchronous output enable eliminating output runt pulse generation and metastability * Standard 32 lead LQFP package
* Industrial temperature range
Functional Description MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the requirement of a negative supply line. Each of the output banks of three differential clock output pairs may be independently configured to distribute the input frequency or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the /2 outputs.
(c) Motorola, Inc. 2001
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MC100ES6226
VCC
Bank A
/1
CLK CLK
/2
Bank B
QA0 QA0 QA1 QA1 QA2 QA2 QB0 QB0 QB1 QB1 QB2 QB2 Bank C QC0 QC0 QC1 QC1 QC2 QC2
MR
FSEL0 FSEL1
Freescale Semiconductor, Inc...
OE
Sync
Figure 1. MC100ES6226 Logic Diagram
VCC
24 QA2 QA2 VCC QA1 QA1 QA0 QA0 VCC 25 26 27 28
23
22
21
20
19
18
17 16 15 14 13 QC0 QC0 QC1 QC1 VCC QC2 QC2 VCC
MC100ES6226
29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9
GND
VCC
CLK
CLK
FSEL0
FSEL1
Figure 2. 32-Lead Package Pinout (Top View)
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MR
OE
VCC
QB0
QB0
QB1
QB1
QB2
QB2
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MC100ES6226
TABLE 1: PIN CONFIGURATION
Pin CLK, CLK OE MR FSEL0, FSEL1 QA[0-2], QA[0-2] QB[0-2], QB[0-2] QC[0-2], QC[0-2] GND VCC I/O Input Input Input Input Output Type LVPECL LVCMOS LVCMOS LVCMOS LVPECL Differential reference clock signal input Output enable Device reset Output frequency divider select Differential clock outputs (banks A, B and C) Function
Supply Supply
GND VCC
Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation
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TABLE 2: FUNCTION TABLE
Control OE Default 0 0 Qx[0-2], Qx[0-2] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses Normal operation See Following Table 1 Qx[0-2] = L, Qx[0-2] =H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses Device reset (asynchronous)
MR FSEL0, FSEL1
0 00
TABLE 3: Output Frequency Select Control
FSEL0 0 0 1 1 FSEL1 0 1 0 1 QA0 to QA2 fQA0:2 = fCLK fQA0:2 = fCLK fQA0:2 = fCLK fQA0:2 = fCLK / 2 QB0 to QB2 fQB0:2 = fCLK fQB0:2 = fCLK fQB0:2 = fCLK / 2 fQB0:2 = fCLK / 2 QC0 to QC2 fQC0:2 = fCLK fQC0:2 = fCLK / 2 fQC0:2 = fCLK / 2 fQC0:2 = fCLK / 2
TABLE 4: ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MC100ES6226
TABLE 5: GENERAL SPECIFICATIONS
Symbol VTT MM HBM CDM LU CIN JA Thermal resistance junction to ambient JESD 51-3, single layer test board Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up immunity 200 2000 1000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2a Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition
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JESD 51-6, 2S2P multilayer test board
JC
Thermal resistance junction to case Operating junction temperatureb (continuous operation) MTBF = 9.1 years
0
110
C
a. b.
Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6226 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6226 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
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TIMING SOLUTIONS
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MC100ES6226
TABLE 6: DC CHARACTERISTICS (VCC = 3.3V 5% and 2.5V 5%, TJ = 0C to +110C)a
Symbol Characteristics Min Typ Max Unit Condition LVCMOS control inputs (OE, FSEL0, FSEL1, MR) VIL VIH IIN VPP VCMR VIH VIL Input voltage low Input voltage high Input Currentb DC differential input voltaged Differential cross point voltagee Input high voltage Input low voltage Input Current VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V 0.8 0.7 2.2 1.7 150 V V A VIN = VCC or VIN = GND Differential operation Differential operation
LVPECL clock inputs (CLK, CLK)c 0.1 1.0 TBD TBD 1.3 VCC-0.3 TBD TBD 150 A VIN = TBD or VIN = TBD Termination 50W to VTT Termination 50W to VTT GND pin All VCC Pins V V
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IIN VOH VOL IGND ICC a. b. c. d. e.
LVPECL clock outputs (QA[2:0], QB[2:0], QC[2:0]) Output High Voltage Output Low Voltage VCC-1.1 VCC-1.8 65 325 VCC-0.8 VCC-1.4 110 400 V V
Supply current Maximum Quiescent Supply Current without output termination current Maximum Quiescent Supply Current with output termination current mA mA
AC characterisitics are design targets and pending characterization. Input have internal pullup/pulldown resistors which affect the input current. Clock inputs driven by LVPECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristic. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification.
TIMING SOLUTIONS
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MC100ES6226
TABLE 7: AC CHARACTERISTICS (VCC = 3.3V 5% and 2.5V 5%, TJ = 0C to +110C)a b
Symbol VPP VCMR VX,OUT VO(P-P) Characteristics Differential input voltagec (peak-to-peak) Differential input crosspoint voltaged Differential output crosspoint voltage Differential output voltage (peak-to-peak) fO < 300 MHz fO < 1.5 GHz fO < 2.7 GHz Input Frequency Propagation Delay CLK to Qx[] Output-to-output skew (within QA[2:0]) (within QB[2:0]) (within QC[2:0]) (within device) (part-to-part) Min 0.2 1.0 VCC-1.45 0.45 0.3 TBD 0 475 500 11 12 4 0.72 0.55 0.37 Typ 0.3 Max 1.3 VCC-0.3 VCC-1.1 0.95 0.95 0.95 3000e 800 25 25 20 60 325 TBD TBD 48 45 49 47.5 0.05 2.5T + tPD 3T + tPD 50 50 50 50 52 55 51 52.5 200 4.5T + tPD 5T + tPD % % % % ns ns ns 20% to 80% T=CLK period T=CLK period Unit V V V V V V MHz ps ps ps ps ps ps Differential Differential Condition
fCLK tPD tsk(O)
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tsk(PP) tJIT(CC)
Output-to-output skew
Differential FSEL0 = FSEL1 FSEL0 FSEL1 DCfref= 50%
Output cycle-to-cycle jitter single frequency configuration /1//2 frequency configuration Output duty cycle Qx = /1, fO < 300 MHz Qx = /1, fO > 300 MHz Qx = /2, fO < 300 MHz Qx = /2, fO > 300 MHz
DCO
tr, tf tPDLf tPLDg a. b. c. d.
Output Rise/Fall Time Output disable time Output enable time
e. f. g.
AC characterisitics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. The MC100ES6226 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay OE assertion to output enabled (active).
CLK CLK
50% OE tPDL (OE to Qx) tPLD (OE to Qx) Outputs disabled
Qx Qx
Figure 3. MC100ES6226 output disable/enable timing
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MC100ES6226
Differential Pulse Generator Z = 50W
ZO = 50
ZO = 50
RT = 50 VTT
DUT MC100ES6226
RT = 50 VTT
Figure 4. MC100ES6226 AC test reference
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APPLICATIONS INFORMATION
Maintaining Lowest Device Skew The MC100ES6226 guarantees low output-to-output bank skew of 35 ps and a part-to-part skew of max. TBD ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6226 is a mixed analog/digital product. The differential architecture of the MC100ES6226 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
VCC 33...100 nF 0.1 nF
VCC MC100ES6226
Figure 5. VCC Power Supply Bypass
TIMING SOLUTIONS
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MC100ES6226
NOTES
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MC100ES6226
NOTES
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TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MC100ES6226
NOTES
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MC100ES6226
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B
-U- V P AE
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B1
8
DETAIL Y
17
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS
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GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z- MOTOROLA
Freescale Semiconductor, Inc.
MC100ES6226
Freescale Semiconductor, Inc...
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E Motorola, Inc. 2001.
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